Semester | Mand. | Option | Filières |
E | x | ||
MA2, MA4 | x | ||
MA2, MA4 | x | A B C | |
MA2, MA4 | x | A D | |
MA2, MA4 | x | A |
Lecture | 2 weekly |
Project | 2 weekly |
Study plan | Semester | Mand. | Option | Filières |
Cyber security 2019-20 | MA2 | x | ||
Cyber security 2019-20 | MA4 | x | ||
Génie électrique et électronique 2019-20 | MA2 | x | A D | |
Génie électrique et électronique 2019-20 | MA4 | x | A D | |
Informatique 2019-20 | MA2 | x | A | |
Informatique 2019-20 | MA4 | x | A | |
Mineur : Science, Technology and Area Studies (STAS) - filière Chine 2019-20 | E | x | ||
Robotique 2019-20 | MA2 | x | A B C | |
Robotique 2019-20 | MA4 | x | A B C | |
Systèmes de communication 2019-20 | MA2 | x | A | |
Systèmes de communication 2019-20 | MA4 | x | A |
Cursus | Sem. | Type |
---|---|---|
Computer science | MA2, MA4 | Opt. |
Cybersecurity | MA2, MA4 | Opt. |
Electrical and Electronical Engineering | MA2, MA4 | Opt. |
Mineur STAS Chine | E | Opt. |
Robotics | MA2, MA4 | Opt. |
SC master EPFL | MA2, MA4 | Opt. |
During this course, response time measurements of interrupts are studied in laboratories, such as for example: the influence of dynamic memories, cache memories, compilation flags. Interrupts response time measurements, task commutations and synchronizations primitives are carried out on an embedded system based on an FPGA.
The course includes the study of embedded systems management models through polling, interrupts and using a real time kernel with its task management and synchronization primitives.
Specialized programmable interfaces are implemented in VHDL to help with these measurements. A real time kernel is studied and used during the labs. An acquisition system is implemented and the gathered data is transmitted by a Web server. To ensure the real time acquisition and reading by the Web server, a multiprocessor system is developed and implemented on an FPGA.
An Accelerator designed in VHDL makes it possible to facilitate the optimization of functions through hardware on an FPGA. Cross development tools are used.
Each topic is treated by a theoretical course and an associated laboratory. The laboratories are realized on an FPGA board including a hardcore multiprocessor. A real time operating system is studied and used with the laboratories.
Real Time, FPGA, SOC, microprocessor, hardware accelerator, custom instruction, Real Time OS
Introduction to computing systems, Logic systems, Computer architecture
Embedded Systems, Real time Programming
Programmable Logic Architecture (FPGA), Computer Architecture, VHDL, C programming, Real Times basic knowledge (semaphor, synchronization)
Ex cathedra, laboratories and a mini-project
Continuous control with reports and oral presentation
all labs 50% + final mini-project 50%
Teaching notes and suggested reading material.
Specialized datasheets (ie.ex. FPGA et specific microcontrollers) and standards.
Slides and documents on moodle
optionnel
optionnel
Cours
Lecture
Heure(s) hebdo x 14 semaines
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Projet
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Pendant le semestre
During the semester
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Session summer
ETE
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Heure(s) hebdo x 14 semaines
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Projet
Project
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Hour(s) per week x 14 weeks
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ETE
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Cours
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ETE
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ETE
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Projet
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Hour(s) per week x 14 weeks
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Pendant le semestre
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Session summer
ETE
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Cours
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Heure(s) hebdo x 14 semaines
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H hebdo
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Projet
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Pendant le semestre
During the semester
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Session summer
ETE
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Heure(s) hebdo x 14 semaines
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Projet
Project
Heure(s) hebdo x 14 semaines
Hour(s) per week x 14 weeks
H hebdo
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Pendant le semestre
During the semester
Session été
Session summer
ETE
ETE
optionnel
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Cours
Lecture
Heure(s) hebdo x 14 semaines
Hour(s) per week x 14 weeks
H hebdo
H hebdo
Projet
Project
Heure(s) hebdo x 14 semaines
Hour(s) per week x 14 weeks
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Pendant le semestre
During the semester
Session été
Session summer
ETE
ETE
optionnel
optionnel
Cours
Lecture
Heure(s) hebdo x 14 semaines
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Projet
Project
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Hour(s) per week x 14 weeks
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Pendant le semestre
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Session summer
ETE
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Cours
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H hebdo
Projet
Project
Heure(s) hebdo x 14 semaines
Hour(s) per week x 14 weeks
H hebdo
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Pendant le semestre
During the semester
Session été
Session summer
ETE
ETE
optionnel
optionnel
Cours
Lecture
Heure(s) hebdo x 14 semaines
Hour(s) per week x 14 weeks
H hebdo
H hebdo
Projet
Project
Heure(s) hebdo x 14 semaines
Hour(s) per week x 14 weeks
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During the semester
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JS_fin
CODE140502511
BOOLEAN_Symbol
1
BaliseJS_debut
\x5brho\x5d
BaliseJS_fin
Balise_debut
[rho]
Balise_fin
FO_debut
[inline]=ρ
FO_fin
HTML_debut
ρ
HTML_fin
JS_debut
\x26#961;
JS_fin
CODE140504636
BOOLEAN_Symbol
1
BaliseJS_debut
\x5bRHO\x5d
BaliseJS_fin
Balise_debut
[RHO]
Balise_fin
FO_debut
[inline]=Ρ
FO_fin
HTML_debut
Ρ
HTML_fin
JS_debut
\x26#929;
JS_fin
CODE148292791
BOOLEAN_Symbol
BaliseJS_debut
\x5bepsilon\x5d
BaliseJS_fin
Balise_debut
[epsilon]
Balise_fin
FO_debut
[inline]=ε
FO_fin
HTML_debut
ε
HTML_fin
JS_debut
\x26#949;
JS_fin
CODE169976220
BOOLEAN_Symbol
BaliseJS_debut
\x5blig\x5d
BaliseJS_fin
Balise_debut
[lig]
Balise_fin
FO_debut
[inline]=›  
FO_fin
HTML_debut
›  
HTML_fin
JS_debut
\x26#x203A;\x26#160;\x26#160;
JS_fin
CODE148292899
BOOLEAN_Symbol
BaliseJS_debut
\x5bEPSILON\x5d
BaliseJS_fin
Balise_debut
[EPSILON]
Balise_fin
FO_debut
[inline]=Ε
FO_fin
HTML_debut
Ε
HTML_fin
JS_debut
\x26#917;
JS_fin
BALISETXT_SAUT
BOOLEAN_Symbol
BaliseJS_debut
\x5bbr\x2f\x5d
BaliseJS_fin
Balise_debut
[br/]
Balise_fin
FO_debut
FO_fin
HTML_debut
<br/>
HTML_fin
JS_debut
\x3cbr\x2f\x3e
JS_fin